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proFPGA Debugging with EXOSTIV │ 快速靈活的除錯方案

Product Overview

In close collaboration with our partner EXOSTIV™ LabsPRO DESIGN offers a debugging tool which has a flexible standard and custom connectivity solutions: Low (micro-)HDMI connector for custom boards and FMC, SFP+ and QSFP+ standard connectivity for any prototyping board.

EXOSTIV™ is an innovative debug solution for FPGA boards. It provides simulator-like visibility – up to 200,000 times more than JTAG-based tools – and fast debug turnaround time for standard and custom FPGA boards. Unlike software-based techniques and emulation, EXOSTIV™ is used on the target or prototyping boards running at speed of operation. It provides an extended visibility on internal nodes over large periods of time – and this, with a minimal impact on the FPGA resources.

EXOSTIV IP uses the MGTs (Multi-Gigabit Transceivers) to flow captured data out of the FPGA to an external memory. EXOSTIV IP supports repeating captures of up to 32,768 internal nodes simultaneously at the FPGA’s speed of operation (16 data sets x 2,048 bits*).

EXOSTIV IP provides dynamic multiplexer controls to capture even more data sets without the need to recompile. Dynamic ON/OFF controls of data sets let you select the data set and preserve the MGT’s bandwidth for when deeper captures of a reduced set of data is required.

EXOSTIV Probe provides up to 8 Gigabyte memory to receive and store data captured from the FPGA. This USB 3.0 Super Speed device establishes the communication channel between the EXOSTIV Application and the IP. EXOSTIV Probe provides multiple physical connection types with the target board that holds the FPGA under test. From 1 to 4 Gigabit Transceivers (up to 12.5 Gbps each) can be used over either SFP/SFP+ or HDMI connectors and cables.

EXOSTIV Dashboard is composed of the Core Inserter and the Analyzer.

EXOSTIV Core Inserter manages sets up the configuration IP and inserts it at RTL or synthesis level into the design. To do this, it establishes a communication link with the FPGA vendor tool suite.

EXOSTIV Analyzer manages data captures from the target design. It provides tools and controls to view, analyze and export the captured data. EXOSTIV Analyzer includes MYRIAD, the industry’s first waveform viewer capable of handling terabytes of waveform data.

 

Reach internal nodes Extract trace Control & Analyze
Up to 16 capture units
Up to 16 data groups per CU
1 trigger + 1 qualification unit per CU
Up to 2.048 nets per data group
IP RAM does not grow with capture size
Sampling @ operating system speed
Up to 8 GB for trace storage
Up to 4 x 12.5 Gbps bandwidth
Uses FPGA Transceivers
Custom, SFP+, QSFP+ and FMC connectivity
Downstream channel for IP control
USB 2.0 or USB 3.0 connection with workstation
IP configuration & insertion
Trigger and data filter set up
IP communication and control
Trace reception and encoding
Advanced waveform viewer

 

  產品文件:proFPGA 產品總覽 (EN) 

 

 
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proFPGA CUT │ FPGA分區工具

Product Summary Multi-FPGA Partitioning

The new proFPGA Cut is a perfect extension to the proFPGA Product Portfolio. The Software includes a guided partitioning tool that handels all required tasks from importing RTL files till exporting it for synthesis and place & route. In Addition its is designed to reduce the design implementation time to a minimum. The proFPGA Cut software is optimized for proFPGA hardware and takes full advantage of the system’s modular and flexible interconnection architecture. Besides the GUI mode, the tool also offers a command line mode which allows the user to script all processes and to fully integrate it into its automated design flow.

The proFPGA systems handle complex ASIC and SoC Designs up to 2 Billion ASIC gates and give design and verification engineers unprecedented speed for high-speed verification and bug hunting to shorten the time to market by eliminating costly re-spins and by providing early prototypes for software development and/or to end customers.
Because of the fast-growing design sizes and the increasing number of required FPGAs, design bring-up and design partitioning are very challenging and time consuming tasks.

Due to the fact that the performance is the most important and critical factor, PRO DESIGN pursues with its new proFPGA Cut tool a different approach. Instead of offering a completely automated “push button” flow with limited control, proFPGA Cut guides the user through the multi-fpga partitioning process step by step from importing RTL to the export to the synthesis tool. Consequently, the user has still full control over the design and the tool supports him to shorten this usually time consuming and complex process. proFPGA Cut offers the insertion of pin multiplexing IPs, logic optimization, constraints setting, conversion of multi-point interconnections into point-to-point interconnections, semi-automated movement of instances/ nets, the possibility of scripting etc.

proFPGA CUT - Visualizer
The easy-to-use software guides the user step-by-step through the design implementation flow, which gives him a structured overview. A tree structure is used to display the design hierarchy. All external access ports (IOs) are shown and can be mapped to physical pins. Furthermore the visualizer displays all design interconnections between FPGAs and how they are physically mapped. In addition, proFPGA CUT can handle different FPGA technologies and a combination of these.

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proFPGA CUT - Main Window

With the design flow view on the left, schematic view on the right and terminal outputs at the bottom, proFPGA CUT is clearly structured.

 

proFPGA CUT - Schematic View

The Schematic Window displays a complete module
(split into pages)

 

  
  

proFPGA CUT - Ressources Window

The design statistics window provides feedback about the required resources of the design and the available resources of the hardware. If no hardware database is loaded only the design resources will be displayed.

 

proFPGA CUT - Cone View

The Cone Window displays schematic excerpts (paths, cones, etc.) and is used for Incremental Schematic Navigation. It allows interactive incremental is closure of the schematic, even across hierarchy borders (giving a kind of “flat-view” on the database).

 

  
  

proFPGA CUT - Move Instances

Window to define destination FPGAs for selected design parts, which should be moved.

 

proFPGA CUT - Pin multiplexing Schemes

IC (interconnection) schemes are especially used to implement multiplexing. Thus, it is necessary to perform this step when the design uses more interconnections between two FPGAs than the hardware provides. Different interconnection schemes can be created for one design, including pin multiplexing factor, data rate, IOSTANDARD and different
clocking schemes.

 

  
  

proFPGA CUT - Synthesize Design Files

At first the user needs to define all input files for the design and the design toplevel. Those can bei either in Verilog, System Verilog or VHDL.

 

  產品文件:proFPGA 產品總覽 (EN) 

 

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proFPGA Builder │ 輕鬆建模並建立系統架構

Product Summary

The proFPGA Builder software provides a powerful environment to create and run user FPGA designs. It is capable of automatically detecting the physical board assembly and generating the complete code framework for multi-FPGA HDL designs, including all scripts for simulation, synthesis, and running the design.

It also can generate automatically the required board description files and board architecture information for partitioning tools. It offers easy-to-use visual help during pin resource planning. With the secure system launch mode, the proFPGA Builder automatically confirms compatibility between actual and intended physical board assembly. The natural 3D visualization helps locating physical ori- gins of system information and checking results

Technical highlights

  • 3D visualization of system architecture
  • Easy modeling and configuration of system architecture
  • Visual pin resource and board connection planning
  • Automatically detecting of physical board assembly
  • Generating complete code framework HDL designs
proFPGA Builder Software
Supported platforms Red Hat Enterprise Linux (RHEL), CentOS 5/6
Windows 7, 64bit
Typical system requirements Windows 7 32/64 bit or Red Hat Enterprise Linux (RHEL), CentOS 5/6
  產品文件:proFPGA 產品總覽 (EN) 

 

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proFPGA DMBI │ 系統設置和 FPGA 配置

Overview

The proFPGA DMBI (Device Message Box Interface) is the gate to the proFPGA prototyping system. It is responsible for the System setup, FPGA configuration and for the User communication. The proFPGA DMBI supports various high-speed communication standards, like PCI, Ethernet and USB2.0. With its simple script based system configuration and launch technique, it allows quick and reproducible test runs. For a comfortable application the proFPGA System can be configured without a host PC by inserting a prepared USB stick into the USB connector.

The flexible DMBI Communication System offers a high bandwidth and low latency integration of both, user software applications and user HDL designs. DMBI is shipped with a large toolbox for debugging and data exchange with user designs. It supports full integration into HDL simulators, making debugging of whole applications easy.

The communication between Host and Slave is based on a point to point communication. In order to have a good overview of the modules, the proFPGA DMBI (MMI 64) is structured in a tree architecture with Host as a root. In addition it supports an automatic identification of modules. The following modules are delivered as HDL modules:

  • Register Interface -> responsible for reading and writing registers

  • AXI Master Interface

  • AHB Master Interface

  • Upstream Interface -> responsible for streaming data to the host

  產品文件:proFPGA 產品總覽 (EN)